This design would not be possible without Ken Shirriff who reverse-engineered some major portions of Z80 from the picture of a die. These are the portions of the A-Z80 design that are based on his work:
- PLA table: http://arcfn.com/files/z80-pla-table.html The table from his blog was taken as-is; I even kept his row numbering for cross-checking. The “z80_pla_checker” tool (in the tools directory) reads this table and ultimately generates a pure Verilog source which A-Z80 is based on.
- ALU unit: http://www.righto.com/2013/09/the-z-80-has-4-bit-alu-heres-how-it.html
- ALU flags module is strongly inspired by the schematic on Ken’s blog “Reverse-engineering the flag circuits in the 8085 processor”. Since Federico Faggin designed both 8085 and Z80, I assumed the basic principles he deployed would be similar, so the circuit can’t be that different between those two processors.
- Address latch and the incrementer: http://www.righto.com/2013/11/the-z-80s-16-bit-incrementdecrement.html
The design was also guided by the following:
- Zilog patents:
- Undocumented instructions documented (“z80-documented-v0.91“) by Sean Young
- Text on WZ register behavior (“memptr_eng.txt“)
- Mostek Z80 Technical Manual (“z80-mostek.pdf“) has timings, opcode execution phases and some other good, hard-to-find stuff
- Z80 Interrupt Structure (“z80-interrupts.pdf“) timings and interrupts
- Official Zilog Z80 Users Manual
- Here are handy Z80 Opcode Tables that I created
- Fully debugged Instruction List with T-States – this is based on the original tables, but I corrected a number of typos and added instruction’s T-States
- My own reverse-engineering of various smaller sections of a Z80 die
… and the wealth of information (start at http://www.z80.info), source code of various emulators, and several existing Verilog FPGA implementations.
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