In this blog I will show you how to interface an Atari-style joystick to the Altera DE1 FPGA board running a Spectrum implementation, how to change the ROM to enable you to input some game-cheat pokes and a few games I eventually completed using this setup.
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Category: Retro
Stuff from the past.
The A-Z80 CPU
This article contains a brief overview and a background of the A-Z80 CPU created for FPGA boards and a ZX Spectrum implementation tied to it.
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ZX Spectrum on FPGA using A-Z80 CPU
In the last article I presented a different way of architecturally modelling a Zilog Z80 processor. It is time to do something really useful with it and what could be better than reliving the past for a moment? Let's recreate an old computer and load in and play some games!
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Z80 Library
This is a list of a some hard to find publications on the Z80 CPU.
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A Z80 : References
This design would not be possible without Ken Shirriff who reverse-engineered some major portions of Z80 from the picture of a die. These are the portions of the A-Z80 design that are based on his work:
A Z80 : The Soul
In the first post I described the sequencer, a circuit that provided discrete timing signals to space operations apart. In the second post I mentioned the Timing matrix that was run by these signals and orchestrated a dance of control signals in time.
This article is about making it all alive and kicking within an FPGA solution.
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A Z80 : The Mind
In the last article I described the sequencer, which is the heart of a CPU, and a few other blocks that perform various tasks. But how is it all orchestrated to perform useful work?
Enter the PLA and the Timing matrix - the mind of a CPU.
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A Z80 : The Heart
Click on any image to open a higher-resolution version.
This is how it all works.
The sequencer is "the heart" of a CPU. It gets the external clock which in turn toggles two rows of flip-flops that generate machine cycles (M-cycles) and clock periods (T-states).
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A Z80 From the Ground Up
A-Z80 is a conceptual implementation of the venerable Zilog Z80 processor targeted to synthesize and run on a modern FPGA device. It differs from the existing (mostly Verilog) Z80 implementations in that it is designed from the ground-up through the schematics and low-level gates.
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The Anatomy of a Z80 Gate
Data bus on the Z80 processor is 8 bits wide. Data bus wires carrying information within the chip itself do not simply connect to package pins and out to the world - the gate circuitry of each bit is quite complex. This article presents a transistor level schematic of a data bit’s gate which I reverse-engineered from a die photograph.
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