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This article contains a brief overview and a background of the A-Z80 CPU created for FPGA boards and a ZX Spectrum implementation tied to it.

(You can find the Russian translation of this article here: https://howtorecover.me/z80-s-nulya)

...continue reading "The A-Z80 CPU"

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A-Z80 is a conceptual implementation of the venerable Zilog Z80 processor targeted to synthesize and run on a modern FPGA device. It differs from the existing (mostly Verilog) Z80 implementations in that it is designed from the ground up through the schematics and low-level gates.

...continue reading "A Z80 From the Ground Up"

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The data bus on the Z80 processor is 8 bits wide. Data bus wires carrying information within the chip itself do not simply connect to package pins and out to the world - the gate circuitry of each bit is quite complex. This article presents a transistor-level schematic of a data bit’s gate which I reverse-engineered from a die photograph.

Data pins (D0-D7) carry arguably the most complex signals on the Z80 since they are both bi-directional and capable of tri-stating. They are located around the +5V pin – four of them on each side. This is a microphotograph of a gate of one of the data pins which we will look at more closely today – a pin for a data line D6.

...continue reading "The Anatomy of a Z80 Gate"

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After reading excellent Ken Shirriff's blog on reverse-engineering parts of the Z80 CPU, I decided to learn how to decipher some of the chip die-shots myself. It turns out not to be that difficult if you follow certain guidelines which I will describe in this post.

Start with a good and clean die-shot. Although the Visual 6502 team had a good one, it was somewhat grainy and I've found a much cleaner version here. There is a slight difference in masks, but the functions are the same. In fact, it may even help to look at several versions when trying to decipher the layout.

...continue reading "Z80 Instruction Register deciphered"

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In my previous post, I described an Arduino dongle and the software that can be used to clock a Z80 CPU and dump the states of its buses and pins while executing a controlled set of test cases.

Here I show a trace of every single Z80 instruction as run by that setup. I also outlined some of the tests created manually that clarified a few situations which were not too obvious (to me) after reading various pieces of documentation.

...continue reading "ZiLOG Z80 (un)documented behavior"